INTERFACE


Come and experience the total solution of TFE.

ATE / ASB BOARD

Test Load Board Design

  Schematic Design Tool: Or-Cad, Cadance Allegro concept HDL
  Design Tool: Allegro (PCB Editor, APD), PADS
  Creates net-list in the design file after completing load BD design and schematic ECO (back-annotation)
  Detects a design error after comparing the created net list to the schematic’s Ch list

Soc Design

  Schematic Tool: Or-Cad, Cadance Allegro concept HDL
  Design Tool: Allegro Layout, Power PCB
  Library Standardization (LMS Development), Part Matching System
  EMI / EMC Consulting, PI/SI Simulation
  Application of High Speed and Impedance Matching Rule
  Build-Up (0.35Pitch) Design and Fabrication



BURN-IN BOARD

Normal Burn-In Board

THB Test
(Temperature Humidity Bias)

High-Speed Burn in Board

HAST
(High Accelerated Temperature Humidity Test)

Burn-in Board Design

  Schematic Tool : Cadstar Schematic, Or-Cad, Cadance concept HDL
  Design Tool : Allegro Layout, Power PCB, Cadstar

Product

  Normal Burn-In Board

  High Speed Burn-In Board

  THB (Temperature Humidity Bias) Test

  HAST (High Accelerated Temperature Humidity Test)